Enhanced Threshold Gate Fan-in Reduction Algorithms
نویسندگان
چکیده
The paper describes and improves on a Boolean neural network (NN) fan-in reduction algorithm, with a view to possible VLSI implementation of NNs using threshold gates (TGs). Constructive proofs are given for: (i) at least halving the size; (ii) reducing the depth from O(N) to O(logN). Lastly a fresh algorithm which reduces the size to polynomial is suggested.
منابع مشابه
Enhanced Threshold Gate Fan - in Reduction Algorithms 1
The paper describes and improves on a Boolean neural network (NN) fan-in reduction algorithm, with a view to possible VLSI implementation of NNs using threshold gates (TGs). Constructive proofs are given for: (i) at least halving the size; (ii) reducing the depth from O(N) to O(logN). Lastly a fresh algorithm which reduces the size to polynomial is suggested.
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